VMX
VMX supports a special privilege mode referred to as VMX-root mode, which may be used to execute a privileged software component known as hypervisor or security virtual machine monitor (SVMM). The SVMM executes as a host, and has full control of processor and hardware resources. The operating system and corresponding ring/privilege structure, may be run as a guest in VMX non-root mode. In non-root mode, certain instructions and processor events may trigger hardware assisted transitions to VMX Root mode (e.g., exit controls such as virtual machine exits/VMExits), allowing the SVMM to monitor and control access to key CPU and platform resources.
EPT
Extended Page Table (EPT) supported by VTx-2 processors allows the SVMM to specify additional permissions for memory pages. The additional permissions may be enforced by hardware in an OS-independent fashion. When a violation of the permissions occurs, the control may be transferred to the SVMM (e.g., via EPT Violation VMExits), providing the SVMM an opportunity to intervene and trigger further actions.
FIG. 1 shows how virtual addresses 10 used by applications may be mapped to physical addresses 12 associated with a guest OS using an OS page-table 14. The guest physical addresses 12 may in turn be mapped to actual physical addresses 16 with the help of an EPT 18. The EPT 18 may specify permissions (e.g., set by the SVMM, which has a higher privilege level than the OS) for physical pages used by the guest OS. The EPT 18 may also carry translations of guest-physical addresses to host physical addresses.
VTx along with EPT may therefore facilitate monitoring and access control of key processor/platform resources such as control registers (CRs), mode specific registers (MSRs), base address registers (BARs), memory mapped input/output (MMIO) registers, extended feature enable registers (EFERs), specific memory regions, and so forth.
Although solutions may be described herein in the context of a LINUX operating system, the solutions are not specific to LINUX and may be used on other operating systems in a similar manner.
Example pre-conditions:                A boot loader/flow may be modified to load SVMM before the OS. The SVMM may run at a higher privilege in VMX-root. The OS may run in a de-privileged mode/state as a guest.        SVMM virtual machine control structure (VMCS) controls and an EPT may be setup appropriately to cause/trigger VMExits on access to monitored assets.        A kernel may be modified to support platform security hooks and delivery of access events        
A platform security component may be loaded, wherein the platform security component may and register access control callbacks with the kernel.
FIG. 2 shows an example sequencing in a security stack as described herein. In the illustrated example, an SVMM 24 operates between a platform 22 (22a-22g) and an OS 20. The platform 22 may include various non-OS managed resources such as, for example, a CR0 22a (e.g., control register zero), a CR4 22b (e.g., control register four), an EFER 22c (e.g., extended feature enable register), one or more MSRs 22d (e.g., mode specific registers), an MMIO register 22e (e.g., memory mapped input/output register), one or more BARs 22f (e.g., base address registers), a display 22g (e.g., liquid crystal display/LCD, organic light emitting diode/OLED display, touch screen, etc.), and so forth.
Example Sequencing:
1. The OS 20 (e.g., executing on a host processor/CPU) accesses a monitored resource or asset of the platform 22, wherein the resources/assets of the platform 22 are non-OS managed resources/assets. The display 22g may visually present information related to the attempt by the OS 20 to access the platform resource.
2. Hardware of the platform 22 transitions control to the SVMM 24 (e.g., via VMExit).
3. The SVMM 24 injects an access event into a guest kernel 26.
4. An extension component 27 of the guest kernel 26 invokes a previously registered policy callback to check the policy decision.
5. A platform security component 28 (e.g., policy code) communicates an action to the guest kernel 26.
6. The guest kernel 26 takes the specified action (e.g., announce/alert/panic, allow, skip, log, etc.) directly or using assistance provided by the SVMM 24.
The illustrated sequencing therefore provides policy based, hardware assisted mandatory access control of processor/platform assets.
FIG. 3 shows a method 30 of operating a security assist apparatus. The method 30 may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic such as, for example, programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), in fixed-functionality logic hardware using circuit technology such as, for example, application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof. For example, computer program code to carry out operations shown in method 30 may be written in any combination of one or more programming languages, including an object oriented programming language such as JAVA, SMALLTALK, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages.
Illustrated processing block 31 provides for registering one or more policy callbacks with respect to a platform resource. Each policy callback may generally include a piece of executable code that is passed as an argument to other code, which is expected to call back (e.g., execute) the argument at some convenient time. Illustrated block 32 detects an attempt by an operating system (OS) to access the platform resource, wherein block 34 may inject, in response to the attempt, an access event into a platform security component via a guest kernel associated with the OS. The attempt may be detected with respect to one or more EPT permissions and/or virtual machine exit controls (e.g., VMExits) set by an SVMM and injecting the access event into the platform security component may include invoking a previously registered policy callback.
Block 36 may provide for responding to the attempt in accordance with a policy response from the platform security component. Block 36 may include, for example, determining whether to one or more of permit the attempt (e.g., grant or deny), log the attempt, announce the attempt (e.g., trigger an alert/alarm), etc., or any combination thereof. As already noted, the attempt may be an attempt to access a non-OS managed resource such as, for example, a control register, mode specific register, base address register, MMIO register, extended feature enable register, etc., or any combination thereof.
FIG. 4 shows a security assist apparatus 38 (38a, 38b). The apparatus, which may include logic instructions, configurable logic, fixed-functionality logic, etc., or any combination thereof, may generally implement one or more aspects of the method 30 (FIG. 3), already discussed. In the illustrated example, a resource monitor 38a detects an attempt by an OS to access a platform resource such as, for example, a control register, mode specific register, base address register, MMIO register, extended feature enable register, etc., or any combination thereof. The apparatus 38 may also include an extension component 38b communicatively coupled to the resource monitor 38a, wherein the extension component 38b is configured to inject, in response to the attempt, an access event into a platform security component. Moreover, a guest kernel (not shown) associated with the OS may respond to the attempt in accordance with a policy response from the platform security component.
The resource monitor 38a may detect the attempt with respect to one or more EPT permissions set by a SVMM. Additionally, the extension component 38b may invoke a previously registered policy callback to inject the access event into the platform security component. In this regard, the extension component 38b may register one or more policy callbacks with respect to the platform resource. Moreover, the guest kernel may determine whether to one or more of permit the attempt, log the attempt or announce the attempt based on the policy response.
FIG. 5 illustrates a processor core 200 according to one embodiment. The processor core 200 may be the core for any type of processor, such as a micro-processor, an embedded processor, a digital signal processor (DSP), a network processor, or other device to execute code. Although only one processor core 200 is illustrated in FIG. 5, a processing element may alternatively include more than one of the processor core 200 illustrated in FIG. 5. The processor core 200 may be a single-threaded core or, for at least one embodiment, the processor core 200 may be multithreaded in that it may include more than one hardware thread context (or “logical processor”) per core.
FIG. 5 also illustrates a memory 270 coupled to the processor core 200. The memory 270 may be any of a wide variety of memories (including various layers of memory hierarchy) as are known or otherwise available to those of skill in the art. The memory 270 may include one or more code 213 instruction(s) to be executed by the processor core 200, wherein the code 213 may implement the method 30 (FIG. 3), already discussed. The processor core 200 follows a program sequence of instructions indicated by the code 213. Each instruction may enter a front end portion 210 and be processed by one or more decoders 220. The decoder 220 may generate as its output a micro operation such as a fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals which reflect the original code instruction. The illustrated front end portion 210 also includes register renaming logic 225 and scheduling logic 230, which generally allocate resources and queue the operation corresponding to the convert instruction for execution.
The processor core 200 is shown including execution logic 250 having a set of execution units 255-1 through 255-N. Some embodiments may include a number of execution units dedicated to specific functions or sets of functions. Other embodiments may include only one execution unit or one execution unit that can perform a particular function. The illustrated execution logic 250 performs the operations specified by code instructions.
After completion of execution of the operations specified by the code instructions, back end logic 260 retires the instructions of the code 213. In one embodiment, the processor core 200 allows out of order execution but requires in order retirement of instructions. Retirement logic 265 may take a variety of forms as known to those of skill in the art (e.g., re-order buffers or the like). In this manner, the processor core 200 is transformed during execution of the code 213, at least in terms of the output generated by the decoder, the hardware registers and tables utilized by the register renaming logic 225, and any registers (not shown) modified by the execution logic 250.
Although not illustrated in FIG. 5, a processing element may include other elements on chip with the processor core 200. For example, a processing element may include memory control logic along with the processor core 200. The processing element may include I/O control logic and/or may include I/O control logic integrated with memory control logic. The processing element may also include one or more caches.
Referring now to FIG. 6, shown is a block diagram of a computing system 1000 embodiment in accordance with an embodiment. Shown in FIG. 6 is a multiprocessor system 1000 that includes a first processing element 1070 and a second processing element 1080. While two processing elements 1070 and 1080 are shown, it is to be understood that an embodiment of the system 1000 may also include only one such processing element.
The system 1000 is illustrated as a point-to-point interconnect system, wherein the first processing element 1070 and the second processing element 1080 are coupled via a point-to-point interconnect 1050. It should be understood that any or all of the interconnects illustrated in FIG. 6 may be implemented as a multi-drop bus rather than point-to-point interconnect.
As shown in FIG. 6, each of processing elements 1070 and 1080 may be multicore processors, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b). Such cores 1074a, 1074b, 1084a, 1084b may be configured to execute instruction code in a manner similar to that discussed above in connection with FIG. 5.
Each processing element 1070, 1080 may include at least one shared cache 1896a, 1896b. The shared cache 1896a, 1896b may store data (e.g., instructions) that are utilized by one or more components of the processor, such as the cores 1074a, 1074b and 1084a, 1084b, respectively. For example, the shared cache 1896a, 1896b may locally cache data stored in a memory 1032, 1034 for faster access by components of the processor. In one or more embodiments, the shared cache 1896a, 1896b may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.
While shown with only two processing elements 1070, 1080, it is to be understood that the scope of the embodiments are not so limited. In other embodiments, one or more additional processing elements may be present in a given processor. Alternatively, one or more of processing elements 1070, 1080 may be an element other than a processor, such as an accelerator or a field programmable gate array. For example, additional processing element(s) may include additional processors(s) that are the same as a first processor 1070, additional processor(s) that are heterogeneous or asymmetric to processor a first processor 1070, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processing element. There can be a variety of differences between the processing elements 1070, 1080 in terms of a spectrum of metrics of merit including architectural, micro architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processing elements 1070, 1080. For at least one embodiment, the various processing elements 1070, 1080 may reside in the same die package.
The first processing element 1070 may further include memory controller logic (MC) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, the second processing element 1080 may include a MC 1082 and P-P interfaces 1086 and 1088. As shown in FIG. 6, MC's 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory locally attached to the respective processors. While the MC 1072 and 1082 is illustrated as integrated into the processing elements 1070, 1080, for alternative embodiments the MC logic may be discrete logic outside the processing elements 1070, 1080 rather than integrated therein.
The first processing element 1070 and the second processing element 1080 may be coupled to an I/O subsystem 1090 via P-P interconnects 1076 1086, respectively. As shown in FIG. 6, the I/O subsystem 1090 includes P-P interfaces 1094 and 1098. Furthermore, I/O subsystem 1090 includes an interface 1092 to couple I/O subsystem 1090 with a high performance graphics engine 1038. In one embodiment, bus 1049 may be used to couple the graphics engine 1038 to the I/O subsystem 1090. Alternately, a point-to-point interconnect may couple these components.
In turn, I/O subsystem 1090 may be coupled to a first bus 1016 via an interface 1096. In one embodiment, the first bus 1016 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the embodiments are not so limited.
As shown in FIG. 6, various I/O devices 1014 (e.g., speakers, cameras, sensors) may be coupled to the first bus 1016, along with a bus bridge 1018 which may couple the first bus 1016 to a second bus 1020. In one embodiment, the second bus 1020 may be a low pin count (LPC) bus. Various devices may be coupled to the second bus 1020 including, for example, a keyboard/mouse 1012, communication device(s) 1026, and a data storage unit 1019 such as a disk drive or other mass storage device which may include code 1030, in one embodiment. The illustrated code 1030 may implement the method 30 (FIG. 3), already discussed, and may be similar to the code 213 (FIG. 5), already discussed. Further, an audio I/O 1024 may be coupled to second bus 1020 and a battery 1010 may supply power to the computing system 1000.
Note that other embodiments are contemplated. For example, instead of the point-to-point architecture of FIG. 6, a system may implement a multi-drop bus or another such communication topology. Also, the elements of FIG. 6 may alternatively be partitioned using more or fewer integrated chips than shown in FIG. 6.